Which elements perform a 16-bit operation

16. 16-bit counter / timer 1

16.1 Features

  • Real 16-bit design
  • Two independent output compare units
  • Output compare register with double buffer
  • An input capture unit
  • Input capture noise reduction
  • Deleting the timer with Compare Match (auto Reload)
  • Glitch-free, phase-correct pulse width modulator (PWM)
  • Variable PWM frequency
  • Frequency generator
  • External event counter
  • Four independent interrupt sources (TOV1, OCF1A, OCF1B and ICF1)

16.2 Overview

Many registers and bits in this document are described in general terms. The index “n” stands for the number of the counter / timer, in this case a 1, and the index “x” stands for the channel of the output compare unit. In a program, however, the precise designations must always be specified, e.g. TCNT1 to access the value of the counter / timer1.

A simple block diagram of the 16-bit counter / timer is shown below. The numbers of the pins depend on the shape of the housing of the component (see pin assignment). The I / O registers, the associated I / O bits and the I / O pins that the CPU can access directly are shown in bold.

16.2.1 Register

The counter / timer register (TCNT1), the output compare register (OCR1A / B) and the input capture register (ICR1) are all 16-bit registers. Access to these registers requires a special procedure, as described in the chapter "Access to the 16-bit registers". The counter / timer control registers (TCCR1A / B) are 8-bit registers that the CPU can access normally. The signals of the interrupt requests (referred to as Int.Req. In the block diagram) are visible in the Timer Interrupt Flag Register (TIFR). All interrupts can be masked individually in the timer interrupt mask register (TIMSK). The last two registers mentioned are not shown in the block diagram as they also contain the bits for other timer units.

The counter / timer can be clocked internally, via a prescaler or by an external clock source on the T1 pin. The clock selection logic specifies by which clock and with which edge the timer increments or decrements its value. The counter / timer is inactive if no clock source is selected. The output of the clock selection logic is referred to as the timer clock clkT1.

The doubly buffered Output Compare Register (OCR1A / B) are constantly compared with the value of the timer. The result of this comparison can be used by the waveform generator to generate a PWM or a variable frequency at the output of the Output Compare Pin (OC1A / B). The event of the comparison match also sets the Compare Match Flag (OCF1A / B), which can be used to trigger an Output Compare interrupt.

The input capture register can specify the value of the counter / timer if this is triggered by an external event on the input capture pin (ICP1) or the analog comparator pins. The input capture unit contains a digital filter to suppress peaks when the value changes.

The top value or the maximum value of the timer can be specified in some operating modes by the OCR1A register, the ICR1 register or by a fixed value. If the OCR1A register is used as a top value in PWM mode, it can no longer be used to generate the PWM output. In these cases, the top value is buffered twice and can therefore be changed while running. If a fixed top value is required, the ICR1 register can be used, whereby the OCR1A register is available for the PWM output.

16.2.2 Definitions

BOTTOMThe counter reaches BOTTOM when it becomes 0000.
MAXThe counter reaches its MAXimum when it becomes FFFFh (65535 decimal)
TOPThe counter reaches TOP when the count reaches an upper limit. The upper value can be set to 00FF, 01FF and 03FF or the value in the OCR1A or ICR1 register. This definition depends on the operating mode.

16.3 Access to 16-bit registers

The TCNT1, the OCR1A / B and the ICR1 register are 16-bit registers which the CPU accesses via the 8-bit data bus. Access must therefore take place in two write or read commands. Therefore the 16-bit timer has an 8-bit buffer in which the high byte of the 16-bit access is temporarily stored. This one shadow register is used for all 16-bit registers of the timer. Access to the low byte triggers the 16-bit read or write command. When the low byte of a 16-bit register is written by the CPU, the high part from the shadow register is also written into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read, the high byte is copied from the register to the shadow register in the same clock cycle.

Not all 16-bit accesses use the shadow register for the high byte: The shadow register is not used when reading the OCR1A / B register.

With a 16-bit write process, the high byte must first be written before the low byte is written. With a 16-bit read process, the low byte is read first, followed by the high byte.

The following example shows the access to the 16-bit timer register, whereby it is assumed that an intermittent interrupt cannot change the shadow register. The same principle can also be used when accessing the OCR1A / B register or the ICR1 register. The "C" example is a 16-bit address.

Code example in assembler
...; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H, r17 out TCNT1L, r16; Read TCNT1 to r17: r16 in r16, TCNT1L in r17, TCNT1H ...
Code example in C
unsigned int i; ... / * Set TCNT1 to 0x01FF * / TCNT1 = 0x1FF; / * Read TCNT1 to i * / i = TCNT1; ...
Note:
  1. See ”About Code Examples” on page 8. For I / O Registers located in extended I / O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I / O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
It is important to note that the access to the low and high byte are two related commands. If an interrupt occurs during the two commands with which the 16-bit register is accessed and one of the 16-bit registers is also accessed during processing, the access interrupted by the interrupt will become faulty. Therefore, in cases in which the main program and an interrupt routine access the 16-bit registers, the interrupts in the main program should be blocked before access.

The following example shows the two related commands for reading out the TCNT1 register. Reading out the OCR1A / B and the ICR1 register can be done according to the same principle.

Code example in assembler
TIM16_ReadTCNT1:; Save global interrupt flag in r18, SREG; Disable interrupts cli; Read TCNT1 to r17: r16 in r16, TCNT1L in r17, TCNT1H; Restore global interrupt flag out SREG, r18 ret
Code example in C
unsigned int TIM16_ReadTCNT1 (void) {unsigned char sreg; unsigned int i; / * Save global interrupt flag * / sreg = SREG; / * Disable interrupts * / _CLI (); / * Read TCNT1 to i * / i = TCNT1; / * Restore global interrupt flag * / SREG = sreg; return i; }
Note:
  1. See ”About Code Examples” on page 8. For I / O Registers located in extended I / O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I / O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembler example writes the value of the TCNT1 back into the register pair R17: R16.

The following example shows the two related commands for writing the TCNT1 register. The OCR1A / B and the ICR1 register can be written using the same principle.

Code example in assembler
TIM16_WriteTCNT1:; Save global interrupt flag in r18, SREG; Disable interrupts cli; Set TCNT1 to r17: r16 out TCNT1H, r17 out TCNT1L, r16; Restore global interrupt flag out SREG, r18 ret
Code example in C
void TIM16_WriteTCNT1 (unsigned int i) {unsigned char sreg; unsigned int i; / * Save global interrupt flag * / sreg = SREG; / * Disable interrupts * / _CLI (); / * Set TCNT1 to i * / TCNT1 = i; / * Restore global interrupt flag * / SREG = sreg; }
Note:
  1. See ”About Code Examples” on page 8. For I / O Registers located in extended I / O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I / O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembler example assumes that the register pair R17: R16 contains the value that is to be written into the TCNT1 register.

If several 16-bit registers are to be written to one after the other and the high byte is the same in all cases, the high byte only needs to be written once.

16.3.1 Multiple use of the shadow register

If several 16-bit registers have to be written with the same high byte, the shadow register only needs to be loaded once. However, it must still be ensured that interrupts do not change the shadow register in between, either by leaving the shadow register untouched by all enabled interrupt routines or by executing the sequence of write accesses with interrupts switched off (cli / be).

16.4 clock sources

The counter / timer can be clocked by an internal or an external source. The clock source is specified with the clock selection bits CS12 to CS10 in the counter / timer control register B (TCCR1B). Details on the clock sources and the prescaler can be found in the chapter "Prescaler for counters / timers 0 and 1".

16.5 Counter unit

The main part of the counter / timer1 is the programmable 16-bit bidirectional counter unit. The block diagram shows the counter unit and its surroundings.
Picture 16-2: Block diagram of the counter
Description of the internal signals:
countIncrements or decrements TCNT1 by 1
directionChoice between increment and decrement
clearClears TCNT1 (all bits zero)
clkT1Counter / timer clock
TOPSignals that TCNT1 has reached the maximum value
BOTTOMSignals that TCNT1 has reached the minimum value (zero)

The 16-bit counter is divided into two 8-bit I / O memories: Counter high (TCNT1H) contains the upper eight bits of the counter, Counter low (TCNT1L) contains the lower eight bits of the counter. The CPU can only access the TCNT1H register indirectly, namely via the shadow register TEMP. The shadow register is filled with the value of TCNT1H when TCNT1L is read and the TCNT1H register is filled with the value of the shadow register when TCNT1L is written. This enables the CPU to change all 16 bits of the counter within the same clock cycle via an 8-bit data bus. (AdÜ .: The C compiler can address 16-bit registers directly in one piece, here via the symbol TCNT1.) It is important to know that there are special cases when writing to the TCNT1 register while the counter is running, in which the outcome becomes unpredictable. These cases are explained in the appropriate places.

Depending on the selected working mode, the counter is cleared, incremented or decremented with the timing of the timer clock clkT1. The clock clkT1 can be generated by an external or internal source; the setting is made with the clock select bits CS12 to CS10. If no clock source is selected CS12 to CS10 = 000, then the counter is stopped. The value of TCNT1 can be accessed at any time, regardless of whether the clock clkT1 is present or not. The writing of the counter by the CPU has priority over all clearing and counting operations of the counter.

A counting sequence is determined by the settings of the waveform generation mode bits (WGM13 to WGM10) in the TCCR1A and TCCR1B registers. There is a fixed relationship between the operation of the counter and the waveform generated at the Output Compare output OC1x.

The timer counter overflow flag (TOV1) is set according to the settings of the WGM1x bits. It can be used to trigger an interrupt.

16.6 Input Capture

The counter / timer works together with an input capture unit, with which external events can be recorded and given a time stamp. The external signal identifies one or more external events that can be applied via the ICP1 pin or, alternatively, can come from the analog comparator unit. The time stamp can then be used to determine the frequency, the duty cycle or other properties of the external signal. The timestamps can also be used to keep a record of the events that have occurred.

The following figure shows the input capture unit. The elements that do not directly belong to the input capture unit are shaded in gray. The "n" in the registers and bit names stands for the number of the counter / timer.

Picture 16-3: Block diagram of the input capture unit
If there is a change in the logic level (event) at the input capture pin (ICP1) or at the analog comparator output (ACO) and this change matches the settings of the edge detector, the acquisition is triggered. When the capture is triggered, the current 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The input capture flag (IVF1) is set in the same clock cycle in which the value of TCNT1 is copied into the ICR1 register. If enabled (TICIE1 = 1) the input capture flag generates an interrupt. The ICF1 flag is automatically cleared when the interrupt routine is executed. Alternatively, the ICF1 flag can also be cleared by writing a logical 1 into the flag.

The 16-bit value is read from the input capture register (ICR1) by first reading the low byte (ICR1L) and then the high byte (ICR1H). The moment the low byte is read, the high byte is copied into the shadow register (TEMP). When the high byte is read, the CPU accesses this shadow register.

The ICR1 register can only be written to if a waveform generation mode is used that uses the ICR1 register to set the TOP value for the counter / timer. In this case the waveform generation mode bits WGM13 to WGM10 must be set before the value can be written into the ICR1 register. When writing, the high byte is first written and stored in the shadow register. When writing the low byte, both bytes are transferred to the ICR1 register.

16.6.1 Trigger source

The main trigger source for the input capture unit is the input capture pin (ICP1). Alternatively, the counter / timer 1 can also use the output of the analog comparator to trigger the input capture unit. The analog comparator is selected as the trigger source by setting the analog comparator input capture bit (ACIC) in the analog comparator control and status register (ACSR). Switching between the trigger sources can result in an acquisition. Therefore, the input capture flag must be cleared after changing the trigger source.

Both the input capture pin and the analog comparator output are scanned using the same technology as the T1 pin (see previous pages). The edge detector is also identical. If the interference suppressor is also activated, additional logic is switched in front of the edge detector, which causes an additional delay of four clock pulses. The input of the interference suppressor and the edge detector are always enabled, except when the timer / counter is working in a waveform generation mode and the ICR1 is used as the TOP value for the counter.

Acquisition can also be triggered by the software by outputting the corresponding level to pin ICP1.

16.6.2 Interference suppression

The interference suppression improves the noise immunity through a simple digital filter. The input of the interference suppression is examined for four clocks and must be the same in all four clocks in order to change the output to the edge detector.

The interference suppression is enabled by setting the Input Capture Noise Canceler Bit (ICNC1) in the Timer / Counter Control Register B (TCCR1B). When the smoke suppressor is enabled, it creates an additional delay of (at least) four clock pulses between the occurrence of the event at the input and the transfer of the counter value into the ICR1 register. The interference suppression uses the system clock and is therefore not influenced by the prescaler.

16.6.3 Use of input capture

The greatest challenge when using the input capture unit is to provide sufficient processor capacity to process the incoming events.The time between two occurring events is particularly critical. If the processor has not yet read the recorded value in the ICR1 register before the next event occurs, the ICR1 register is overwritten with the new value. In this case, the result becomes unusable.

If the input capture interrupt is used, the value of the ICR1 register must be read as early as possible in the interrupt routine. Even if the input capture interrupt has a relatively high priority, the maximum response time depends on the maximum length of the other interrupt routines.

It is not recommended to use the input capture unit if the TOP value is actively changed during work.

Measurements of pulse width external signals require that the edge detection is switched after each acquisition. The edge direction must be switched as soon as possible after reading out the ICR1 register. After changing the edge direction, the input capture flag (ICF1) must be cleared by the software. If only the frequency of the external signal is to be measured, the ICF1 bit does not have to be cleared by the software if the corresponding interrupt routine is used.

16.7 Output Compare

The 16-bit comparator continuously compares the value of the TCNT1 register with the Output Compare Register OCR1A and OCR1B. If the values ​​of TCNT1 and OCR1x are the same, the comparator signals the agreement. If they match, the Output Compare Flag (OPCF1x) is set with the next timer cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an interrupt. The flag is automatically cleared when the interrupt routine is executed. However, it can also be deleted by software by writing a logical 1 into the bit. The waveform generator uses the match signal to generate an output signal according to the settings of the waveform generation mode bits (WGM13 to WGM10) and the compate output mode bits (COM1x1 to COM 1x0). The TOP and BOTTOM signals are used by the waveform generator to handle the special cases of extreme values ​​in some operating modes.

The special properties of the Output Compare Unit A allow the TOP value (i.e. the resolution) of the counter / timer to be determined. In connection with the resolution of the counter, the TOP value determines the period duration of the output signal that the waveform generator generates.

The following figure shows the block diagram of the Output Compare unit. The "n" stands for the number of the counter / timer (ie 1), the "x" stands for the two Output Compare units A and B. The parts that do not directly belong to the Output Compare unit are shaded in gray.

Picture 16-4: Block diagram of the output compare unit
The OCR1x registers are double-buffered when one of the twelve PWM modes is used. In the normal Clear Timer on Compare (CTC) mode, double buffering is switched off. The double buffering is used to synchronize the current count with changing TOP and BOTTOM values ​​in the ORC1x registers. The synchronization prevents the occurrence of asymmetrical PWM pulses and makes the output glitch free.

Accessing the OCR1x registers looks complicated, but it isn't. If the buffering is enabled, the CPU accesses the ORC1x buffer registers; if the buffering is switched off, the CPU then accesses the OCR1x registers directly. The content of the OCR1x register can only be changed by a write command, it is not automatically updated by the counter like the TCNT1 or the ICR1 register. Therefore the high byte does not have to be read via a shadow register. However, it is good practice to always read the low byte first when accessing 16-bit registers. The OCR1x register is written via the shadow register, since all 16 bits are compared continuously. The high byte (OCR1xH) must be written first and is stored in the shadow register (TEMP). If the low byte is then written into the OCR1xL register, the value from the TEMP register is also copied into the OCR1xH register.

The C compiler automatically realizes the 16-bit access correctly when the symbol OCR1x is addressed.

16.7.1 Force Output Compare

In non-PWM modes, the match output of the comparison can also be forced by writing a 1 in the Force Output Compare bit FOC1x. In the case of a forced comparison match, neither the OCF1x flag is set, nor the timer is deleted or reloaded. However, the OCP1x pin is updated as if a real comparison match had occurred. Whether the OCP1x pin is deleted, set or changed is determined by the settings of the COM1x1 to COM1x0 bits.

16.7.2 Blocking of Output Compare when writing to TCNT1

All attempts by the CPU to write to the TCNT1 register block a comparison match that occurs in the next clock cycle, even if the timer is stopped. This enables the OCR1x register to be written with the same values ​​as the TCNT1 register without triggering an interrupt.

16.7.3 Use of the output compare unit

Since writing to the TCNT1 register blocks the comparison match for a timer cycle in every mode, certain risks arise when changing TCNT1 if one of the output compare channels is used, regardless of whether the timer is running or not. If a value is written into the TCNT1 which corresponds to the value of an OCR1x, the comparison will not match, whereby an incorrect output form is generated. The TCNT1 should therefore not be written with the TOP value in PWM modes with variable TOP values. The comparison match for the TOP value would be ignored and the counter would continue to count up to the maximum value FFFF. Conversely, TCNT1 should not be written with the BOTTOM value if the counter is running backwards.

The OC1x register should be set before the corresponding port pin is configured as an output. The easiest way to set the OC1x value is to use the Force-Output-Compare-Bit (FOC1x) in normal mode. The OCR1x registers retain their value even when switching between the waveform generation modes.

It should be noted that the COM1x1 to COM1x0 bits are not double-buffered. Changes to these bits therefore have an immediate effect.

16.8 Compare Match

The compare output mode bits COM1x1 and COM1x0 have two functions. On the one hand, the waveform generator uses the two bits to determine the state of the OCR1x register when the next comparison match. Second, the bits control the output source of the OC1x pin. The following figure shows the simple block diagram of the logic that is influenced by the COM1x1 and COM1x0 bits. The I / O registers, the I / O bits and the I / O pins are shown in bold, whereby of the port control registers DDR and PORT only the part influenced by the bits is shown. When reference is made to the status of the OCR1x, this means the internal register OCR1x and not the OC1x pin. In the event of a system reset, the OCR1x register is set to 0.
Picture 16-5: Block diagram of the Compare-Match-Output-Unit
The general I / O port function is overwritten by the output compare (OC1x) if one of the two bits COM1x1 or COM1x0 is set. However, the direction of the OC1x pin (input or output) is still determined by the data direction register (DDR). The direction bit for the OC1x pins (DDR_OC1x) must be set as an output before the value of OC1x is visible at the output. The overwriting function is basically independent of the selected waveform generator mode. However, there are a few exceptions that can be seen in the tables below.

The design of the output compare pin logic allows the OC1x state to be initialized before the output is enabled. Some COM1x1 / COM1x0 combinations are reserved for later functions (see description of the registers). The two COM1x bits have no influence on the input capture unit.

16.8.1 Compare output and waveform generation

The waveform generator uses the COM1x1 and COM1x0 bits differently in the normal, CTC and PWM modes. In all cases, if both bits are set to 0, no action is triggered in the event of a comparison match. More details in the later tables.

16.9 Operating modes

The operating mode, i.e. the behavior of the counter / timer and the output compare pin, is determined by the combination of the waveform generation mode bits (WGM13 to WGM10) and the compare output mode bits (COM1x1 to COM1x0). The Compare Output Mode Bits do not influence the counting sequence, but the Waveform Generation Mode Bits do. The COM1x1 and COM1x0 bits determine whether the PWM output should be inverted or not. In non-PWM modes, the COM1x1 and COM1x0 bits determine whether the output should be deleted, set or changed if a comparison match occurs.

16.9.1 Normal mode

The simplest operating mode is the normal mode (WGM13 to WGM10 = 000). In this mode the counter always counts up (increment) and is not cleared. When the counter reaches its maximum value (FFFF) it overflows and starts again at its BOTTOM value 0000. In normal mode, the timer overflow flag (TOV1) is set at the moment when the TCNT1 register becomes 0000 again. In this case, the TOV1 flag can be viewed as a 17 bit, but it is only set and not automatically deleted. In combination with the timer overflow interrupt, which automatically clears the TOV1 flag, the resolution of the timer can be significantly expanded by the software. In normal mode, there are no special features to consider, the value of the TCNT1 register can be overwritten at any time.

The input capture unit is easy to use in normal mode. It must be ensured that the maximum time between two external events does not lie outside the resolution of the timer / counter. If this interval is too long, the timer overflow interrupt or the prescaler can be used to increase the resolution for the capture unit.

The Output Compare unit can be used to generate interrupts at the respective counter reading. Generating output frequencies in normal mode is not recommended as it uses too much processor capacity.

16.9.2 Shortened counting cycle

In the Clear Timer on Compare mode (CTC) (WGM13 to WGM10 = 4 or 12) the registers OCR1A or ICR1 are used to manipulate the resolution of the timer. In CTC mode, the counter is cleared when the value of the counter (TNCT1) matches either that of the OCR1A register (WGM13 to WGM10 = 4) or that of the ICR1 register (WGM13 to WGM10 = 12). The two registers OCR1A and ICR1 determine the maximum value of the counter and thus its resolution. This mode allows greater control over the Compare Match output frequency. It also makes it easy to count external events.

The timing diagram of the CTC mode is shown below. The value of the counter (TCNT1) increases until a comparison with OCR1A or ICR1 occurs, then the counter (TCNT1) is cleared.

Picture 16-6: Time course with a shortened counting cycle
The flags OCF1A or ICF1 can generate an interrupt at any point in time when the value of the counter reaches the TOP value specified by the OCR1A or ICR1 register. When the interrupt is enabled, the interrupt routine can be used to change the TOP value. The setting of the TOP value close to the BOTTOM value must be done with caution if the counter is operated with no or a low prescaler, as the CTC mode does not have a double buffer property. If a new value is written into the OCR1A or ICR1 register that is smaller than the current value of the TCNT1, no comparison match is initially recognized. The counter will then initially run up to its maximum value (FFFF) and start again from 0000, only then can a comparison match be recognized. In many cases this behavior is undesirable. An alternative is to use the Fast PWM mode, in which OCR1A forms the TOP value, which is double-buffered.

When generating an output frequency in CTC mode, the OC1A output can be set in such a way that it changes its state with every comparison match by setting the COM1A1 and COM1A0 bits to 1. The OC1A value will not appear on the port pin if the data direction is not set to output (DDR_OC1A = 1). The output wave generated can have a maximum frequency of fOC1A = fclk_I / O/ 2 when OCR1A is set to 0000. In general, the output frequency is determined using the following equation: The variable N stands for the factor of the prescaler (1, 8, 64, 256 or 1024).

fOCnA =fclk_I / O
N(1 + OCRnA)
In normal mode, the TOV1 flag is set in the same clock cycle in which the counter changes from its MAX value to 0000.

16.9.3 Fast pulse width modulation (PWM)

The Fast PWM mode (WGM13 to WGM10 = 5, 6, 7, 14 or 15) offers a high-frequency output wave. The Fast PWM mode differs from the other PWM modes in that it has a simple pulse edge. The counter counts from the BOTTOM value to the TOP value and then starts again with the BOTTOM value. In the non-inverting Compare Output Mode, the Output Compare (OC1x) is set when there is a comparison between the TCNT1 and OCR1x and is deleted when the TOP value is reached. In the inverting Output Compare mode it is exactly the opposite. Due to the single pulse edge, the frequency in Fast PWM mode can be twice as high as in the other PWM modes that work with a double pulse edge. The high frequency of the PWM signal is beneficial for use as voltage regulation, rectification and similar digital-to-analog converter applications. High frequencies allow small external components (coils, capacitors), which can reduce system costs. The PWM resolution in Fast PWM mode can be set to 8-, 9- or 10-bit, or it can be set by the ICR1 or OCR1A. The minimum resolution is 2 bits (ICR1 or OCR1A set to 0003), the maximum resolution is 16 bits (ICR1 or OCR1A set to MAX). The resolution of the PWM in bits can be calculated with the following formula: In the Fast PWM mode the counter is incremented until the counter either has one of the fixed values ​​00FFh, 01FFh or 03FFh (WGM13 to WGM10 = 5, 6, or 7) or reaches the value of ICR1 (WGM13 to WGM10 = 14) or the value of OCR1A (WGM13 to WGM10 = 15). The counter is then cleared with the following cycle of the timer cycle. The time diagram of the Fast PWM mode can be seen in the following picture. It shows the case in which ICR1 or OCR1A specify the TOP value. The value of the TCNT1 is shown as a histogram to show the simple pulse edge. The inverting and non-inverting outputs are also shown. The small horizontal lines on the TCNT1 edge indicate the comparison match between OCR1x and TCNT1. The OC1x interrupt flag is set when a comparison match occurs.
Picture 16-7: Time course with fast pulse width modulation
The timer / counter overflow flag (TOV1) is set every time the counter reaches its TOP value. In addition, the OCF1A or the ICF1 flag are set if the OCR1A or the ICR1 register determine the TOP value. If one of the interrupts is enabled, the interrupt routine can be used to update the TOP and comparison values.

If the TOP value is changed, the program must ensure that the new TOP value is greater than or equal to the value of all comparison registers. If the new TOP value is smaller, there can be no comparison between TCNT1 and OCR1x. If the fixed TOP values ​​are used, the unused bits are masked with 0 when one of the OCR1x registers is written.

The procedure for updating the ICR1 register differs from updating the OCR1A register if this is used to set the TOP value. The ICR1 register is not buffered twice. This means that if the ICR1 is changed to a small value and the counter is operated with no or a small prescaler, there is a risk that the new ICR1 value will be smaller than the current value of TCNT1. The result will be that the counter does not achieve a comparison match before it reaches the TOP value. The counter will then run to the maximum value FFFF, overflow and restart at 0000 before a comparison match occurs. The OCR1A register, on the other hand, is buffered twice. This property allows the OCR1A register to be written to at any time. The new value of the OCR1A is first written into the buffer register and only transferred to the OCR1A comparison register with the clock cycle that follows the reaching of the TOP value by the TCNT1.The new value is accepted at the same time that the TCNT1 is deleted and the TOV1 flag is set.

Using the ICR1 register to define the TOP value is just as useful as working with the fixed values. If the ICR1 register is used for the TOP value, the OCR1A register is available to generate the PWM output on OC1A. Whenever the base frequency of the PWM signal is to be changed during operation, it is better to use the OCR1A register as the TOP value, as it is double-buffered.

In the Fast PWM mode, the comparison units allow the generation of PWM signals on the OC1x pins. By setting the COM1x1 and COM1x0 bits to 2, a non-inverted PWM signal is generated. An inverted PWM signal can be generated by setting COM1x1 and COM1x0 to 3. In order to make the PWM signal visible on the port pin, it must be configured as an output (DDR_OC1X = 1). The PWM signal is generated by setting (clearing) the OC1x register if there is a comparison match between OCR1x and TCNT1 and the OC1x register is cleared (set) in the clock cycle in which the counter is cleared by changing from TOP to BOTTOM.

The frequency of the output signal can be calculated using the following formula:

fOCnxPWM =fclk_I / O
N(1 + TOP)
The variable N stands for the factor of the prescaler (1, 8, 64, 256 or 1024). Extreme values ​​of the OCR1x register represent special cases in the generation of the PWM signal in Fast PWM mode. If an OCR1x register is set to the same value as BOTTOM (i.e. 0000), a narrow peak is generated at the output, which with every TOP + 1 bar occurs. Setting the OCR1x register to the TOP value will result in a constant low or high level at the output (depending on whether inverting or non-inverting output is set).

A frequency with a duty cycle of 50% can be achieved in Fast PWM mode by setting OC1A so that it changes its level with every comparison match (COM1x1 and COM1x0 bits to 1). However, this can only be achieved if OCR1A is used to define the TOP value. The generated output wave can have a maximum frequency of fOC1A = fclk_I / O / 2 when OCR1A is set to 0000. This property is the same as the OC1A toggle in CTC mode, with the exception that the double-buffered Output Compare unit is available in Fast PWM mode.

16.9.4 In-phase PWM

The Phase Correct PWM mode (WGM13 to WGM10 = 1, 2, 3, 10 or 11) offers a phase correct output wave with high resolution. The phase correct PWM mode is based, like the phase an frequenzy correct PWM mode, on a double pulse edge. The counter counts from the BOTTOM value to the TOP value and back again from the TOP to the BOTTOM value. In the non-inverting Compare Output Mode, the Output Compare (OC1x) is deleted if a comparison match between the TCNT1 and OCR1x occurs when counting up and is set if a comparison match occurs when counting down. In the inverting Output Compare mode it is exactly the opposite. Due to the double pulse edge, the frequency in the phase correct PWM mode is lower than in the PWM modes that work with a single pulse edge. Because of the symmetrical properties of the PWM modes with double pulse edge, they are particularly suitable for controlling motors.

The PWM resolution in Phase Correct PWM mode can be set to 8-, 9- or 10-bit, or it can be set by the ICR1 or OCR1A. The minimum resolution is 2 bits (ICR1 or OCR1A set to 0003), the maximum resolution is 16 bits (ICR1 or OCR1A set to MAX). The resolution of the PWM in bits can be calculated with the following formula: In Phase Correct PWM mode the counter is incremented until the counter either has one of the fixed values ​​00FF, 01FF or 03FF (WGM13 to WGM10 = 1, 2, or 3) or the value of ICR1 (WGM13 to WGM10 = 10) or the value of OCR1A (WGM13 to WGM10 = 11). The counter has then reached the TOP value and then changes its counting direction. The value of TCNT1 will be equal to the selected TOP value for one cycle. The timing diagram of the Phase Correct PWM mode can be seen in the following picture. It shows the case in which ICR1 or OCR1A specify the TOP value. The value of the TCNT1 is shown as a histogram to show the double pulse edge. The inverting and non-inverting outputs are also shown. The small horizontal lines on the TCNT1 edge indicate the comparison match between OCR1x and TCNT1. The OC1x interrupt flag is set when a comparison match occurs.

Picture 16-8: Time course with in-phase PWM
The timer / counter overflow flag (TOV1) is set every time the counter reaches its BOTTOM value. If the OCR1A or the ICR1 register determine the TOP value, the OCF1A or the ICF1 flag are set accordingly in the same timer cycle in which the OCR1x register is updated with the double buffered value (with TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.

If the TOP value is changed, the program must ensure that the new TOP value is greater than or equal to the value of all comparison registers. If the new TOP value is smaller, there can be no comparison between TCNT1 and OCR1x. If the fixed TOP values ​​are used, the unused bits are masked with 0 when one of the OCR1x registers is written. As can be seen in the third period in the timing diagram, changing the TOP value during operation can lead to an unbalanced output. The reason for this lies in the time in which the OCR1x register is updated. Because the OCR1x register is updated when the TOP value is reached, a period begins and ends at the TOP value. As a result, the length of the falling edge is determined by the old TOP value, while the length of the rising edge is determined by the new TOP value. If these two values ​​are different, the length of the two edges also differs. The difference in length then leads to the unbalanced output signal.

It is recommended to use the phase and frequency correct PWM mode if the TOP value is to be changed while the counter is running. If a fixed TOP value is used, there is no difference between these two modes.

In the phase correct PWM mode, the comparison units allow the generation of PWM signals on the OC1x pins. By setting the COM1x1 and COM1x0 bits to 2, a non-inverted PWM signal is generated. An inverted PWM signal can be generated by setting COM1x1 and COM1x0 to 3. In order to make the PWM signal visible on the port pin, it must be configured as an output (DDR_OC1X = 1). The PWM signal is generated by setting (clearing) the OC1x register if there is a comparison match between OCR1x and TCNT1 when counting up and the OC1x register is cleared (set) if there is a comparison match between OCR1x and TCNT1 when counting down. The frequency of the output signal can be calculated using the following formula:

fOCnxPCPWM =fclk_I / O
N·TOP
The variable N stands for the factor of the prescaler (1, 8, 64, 256 or 1024). Extreme values ​​of the OCR1x register represent special cases when generating the PWM signal in phase correct PWM mode. If an OCR1x register is set to the same value as BOTTOM, the output remains permanently at low level Setting the OCR1x register to TOP Value will lead to a constant high level at the output (in inverting mode it is exactly the other way around).

If the OCR1A is used to set the TOP value (WGM13 to WGM10 = 11) and COM1A1 and COM1A0 are set to 1, the OC1A output changes with a duty cycle of 50%.

16.9.5 Phase and frequency correct PWM

The Phase and Frequency Correct PWM mode (WGM13 to WGM10 = 8 or 9) offers a phase and frequency correct output wave with high resolution. The phase and frequency correct PWM mode, like the phase correct PWM mode, is based on a double pulse edge. The counter counts from the BOTTOM value (0000) to the TOP value and back again from the TOP to the BOTTOM value. In the non-inverting Compare Output Mode, the Output Compare (OC1x) is deleted if a comparison match occurs between the TCNT1 and OCR1x when counting up and is set if a comparison match occurs when counting down. In the inverting Output Compare mode it is exactly the opposite. Due to the double pulse edge, the frequency in the phase and frequency correct PWM mode is lower than in the PWM modes that work with a single pulse edge. Because of the symmetrical properties of the PWM modes with double pulse edge, they are particularly suitable for controlling motors.

The main difference between the phase correct and the phase and frequency correct PWM mode is the moment in which the OCR1x register is updated with the value from the OCR1x buffer register.

The PWM resolution in phase and frequency PWM mode can be set by the ICR1 or the OCR1A. The minimum resolution is 2 bits (ICR1 or OCR1A set to 0003), the maximum resolution is 16 bits (ICR1 or OCR1A set to MAX). The resolution of the PWM in bits can be calculated using the following formula:

R.PFCPWM =log(TOP+1)
log (2)
In Phase and Frequency Correct PWM mode, the counter is incremented until the counter reaches the value of ICR1 (WGM13 to WGM10 = 8) or the value of OCR1A (WGM13 to WGM10 = 9). The counter has then reached the TOP value and then changes its counting direction. The value of TCNT1 will be equal to the selected TOP value for one cycle. The timing diagram of the Phase and Frequency Correct PWM mode can be seen in the following picture. It shows the case in which ICR1 or OCR1A specify the TOP value. The value of the TCNT1 is to be shown as a histogram around the double pulse edge. The inverting and non-inverting outputs are also shown. The small horizontal lines on the TCNT1 edge indicate the comparison match between OCR1x and TCNT1. The OC1x interrupt flag is set when a comparison match occurs.

Picture 16-9: Time course with phase and frequency correct PWM
The timer / counter overflow flag (TOV1) is set every time the OCR1x register is updated with the value from the buffer (for the BOTTOM value). If the OCR1A or the ICR1 register determine the TOP value, the OCF1A or the ICF1 flag are set accordingly when TCNT1 has reached the TOP value. The interrupt flags can be used to trigger an interrupt each time the counter reaches the TOP or BOTTOM value.

If the TOP value is changed, the program must ensure that the new TOP value is greater than or equal to the value of all comparison registers. If the new TOP value is smaller, a comparison match between TCNT1 and OCR1x can never occur.

The figure shows that, in contrast to the phase-correct PWM mode, the output is symmetrical in all periods. Because the OCR1x register is updated when BOTTOM is reached, the length of the falling and rising pulse edge is always the same. This results in a symmetrical output wave that is always correct in frequency.

Using the ICR1 register to define the TOP value is just as useful as working with the fixed values. If the ICR1 register is used for the TOP value, the OCR1A register is available to generate the PWM output on OC1A. Whenever the base frequency of the PWM signal is to be changed during operation, it is better to use the OCR1A register as the TOP value, as it is double-buffered.

In the phase and frequency correct PWM mode, the comparison units allow the generation of PWM signals on the OC1x pins. By setting the COM1x1 and COM1x0 bits to 2, a non-inverted PWM signal is generated. An inverted PWM signal can be generated by setting COM1x1 and COM1x0 to 3. In order to make the PWM signal visible on the port pin, it must be configured as an output (DDR_OC1X = 1). The PWM signal is generated by setting (clearing) the OC1x register if there is a comparison match between OCR1x and TCNT1 when counting up and the OC1x register is cleared (set) if there is a comparison match between OCR1x and TCNT1 when counting down.

The frequency of the output signal can be calculated using the following formula:

fOCnxPFCPWM =fclk_I / O
N·TOP
The variable N stands for the factor of the prescaler (1, 8, 64, 256 or 1024). Extreme values ​​of the OCR1x register represent special cases when generating the PWM signal in phase and frequency correct PWM mode. If an OCR1x register is set to the same value as BOTTOM, the output remains permanently at low level. Setting the OCR1x register to the TOP value will lead to a constant high level at the output (in inverting mode it is exactly the other way around). If the OCR1A is used to set the TOP value (WGM13 to WGM10 = 9) and COM1A1 and COM1A0 are set to 1, the OC1A output changes with a duty cycle of 50%.

16.10 Timing Diagrams

The counter / timer is constructed synchronously, so the clock signal clkT1 is shown in the following figures as a signal that enables the clock. The figures also show when the interrupt flags are set and the OCR1x registers are updated with the values ​​from the buffer register (only in modes that use double buffering).

The following figure shows the setting of the OCF1x

Picture 16-10: Time course, setting of OCF1x, without prescaler
The following figure shows the same process, but with a prescaler
Picture 16-11: Time course, setting of OCF1x, with prescaler (fclk_I / O/8)
The following figure shows a counting sequence up to the TOP value in different modes. If the phase and frequency correct PWM mode is used, the OCR1x register at BOTTOM is updated. The timing diagram is the same, but TOP has to be replaced by BOTTOM, TOP-1 by BOTTOM + 1, etc. The renaming also applies to the modes that set the TOV1 flag in BOTTOM.
Picture 16-12: Time diagram for counter overflow, without prescaler
The following figure shows the same process, but with a prescaler
Picture 16-13: Time diagram for counter overflow, with prescaler (fclk_I / O/8)

16.11 Register description

16.11.1 TCCR1A - control register A

bit76543210
(0x80)COM1A1COM1A0COM1B1COM1B0--WGM11WGM10TCCR1A
accessR / WR / WR / WR / WR.R.R / WR / W
Starting value00000000
  • Bit 7 and 6 - COM1A1 and COM1A0: Compare Output Mode for channel A
  • Bit 5 and 4 - COM1B1 and COM1B0: Compare Output Mode for channel B
The two bits COM1A1 / COM1A0 and COM1B1 / COM1B0 control the behavior of the two output compare pins OC1A and OC1B. If one of the two bits is set, the OC1x signal is superimposed on the normal I / O function of the pin. In the Data Direction Register (DDR) the corresponding bits for OC1A or OC1B must be set so that the pins are configured as outputs.

If OC1A or OC1B are used as output function, their function depends on the settings of the WGM bits. The following table shows the functions of the COM1nx bits when the WGM bits are set to normal or CTC mode.

Table 16-1: Action for Output Compare in non-PWM operating modes
COM1A1 / COM1B1COM1A0 / COM1B0function
00Normal port function, OC1A / OC1B switched off
01Change to OC1A / OC1B at Compare Match
10Deleting OC1A / OC1B with Compare Match (low level)
11Setting OC1A / OC1B with Compare Match (high level)
Table 16-2: Action at Output Compare with fast PWM(1)
COM1A1 / COM1B1COM1A0 / COM1B0function
00Normal port function, OC1A / OC1B switched off
01WGM = 15: Change to OC1A during Compare Match, OC1B switched off (normal port function)
10Deletion of OC1A / OC1B for Compare Match, setting of OC1A / OC1B for TOP
11Set OC1A / OC1B for Compare Match, delete OC1A / OC1B for TOP
Note:
  1. A special case occurs when OCR1A / OCR1B is set equal to TOP and COM1A1 / COM1B1. In this case, the Compare-Match event is ignored, but deletion or setting to BOTTOM is carried out. See above for details.
Table 16-3: Action at Output Compare with phase and / or frequency correct PWM(1)
COM1A1 / COM1B1COM1A0 / COM1B0function
00Normal port function, OC1A / OC1B switched off
01WGM = 9 or 14: Change to OC1A with Compare Match, OC1B switched off (normal port function)
10Deleting OC1A / OC1B for Compare Match when counting up, setting OC1A / OC1B for Compare Match when counting down
11Set OC1A / OC1B for Compare Match when counting up, delete OC1A / OC1B for Compare Match when counting down
Note:
  1. A special case occurs when OCR1A / OCR1B is set equal to TOP and COM1A1 / COM1B1. See above for details.
  • Bit 1 and 0 - WGM11 and WGM10: Waveform Generation Mode
These bits are to be used in combination with the WGM bits that can be found in the TCCR1B register. The WGM bits control the counting sequence of the counter, the source for the maximum value (TOP) of the counter and the type of output wave generated. The working modes supported by counter / timer 1 are: normal, reduced counting scope (CTC) and three different PWM modes.
Table 16-4: Bit description for the type of vibration generation(1)
modeWGM13WGM12WGM11
(CTC1)
(PWM11)
WGM10
(PWM10)
PWM operating modeTOPWhen should OCR1x be updated?When is the TOV flag set?
00000normal0xFFright awayMAX
10001In-phase PWM 8 bit0x00FFTOPBOTTOM
20010In-phase PWM 9 bit0x01FF
30011In-phase PWM 10 bit0x03FF
40100Reduced counting scopeOCR1Aright awayMAX
50101Fast PWM 8 bit0x00FFBOTTOMTOP
60110Fast PWM 9 bit0x01FF
70111Fast PWM 10 bit0x03FF
81000Phase and frequency correct PWMICR1BOTTOMBOTTOM
91001OCR1A
101010In-phase PWMICR1TOPBOTTOM
111011OCR1A
121100Shortened counting scopeICR1right awayMAX
131101reserved---
141110Fast PWMICR1BOTTOMTOP
151111OCR1A
Note:
  1. The bit names CTC1 and PWM [1: 0] are obsolete and to maintain compatibility with older source code. The new bit names WGM1 [3: 0] should be used in new software.

16.11.2 TCCR1B - control register B

bit76543210
(0x81)ICIC1ICES1-WGM13WGM12CS12CS11CS10TCCR1B
accessR / WR / WR.R / WR / WR / WR / WR / W
Starting value00000000
  • Bit 7 - ICNC1: Interference suppression for input capture
If this bit is set, interference suppression is activated. When the interference suppression is activated, the input of the input capture pin is filtered. The filter function requires four successful equal value samples of the ICP1 pin to change its output. The input capture is therefore delayed by four clocks when the interference suppression is enabled.
  • Bit 6 - ICES1: Edge selection for input capture
This bit determines which edge at the input capture pin ICP1 is necessary to trigger a capture event. If the ICES1 bit is set to 0, a negative / falling edge is used as a trigger, if the ICES1 bit is set to 1, a positive / rising edge is used as a trigger.

If a trigger occurs according to the setting of the bit, the value of the counter is copied into the input capture register ICR1. The event also sets the input capture flag ICF1, which can be used to trigger an interrupt if it is enabled.

If the ICR1 register is used as the TOP value (see WGM bits), the ICP1 pin is switched off and the input capture function is blocked.

  • Bit 5 - Res: Reserved bit
This bit is reserved and is always read as 0. To ensure compatibility with future blocks, the bit should always be written with 0 when the TCCR1B register is written.
  • Bit 4: 3 - WGM1 [3: 2]: Operating mode of the vibration generation
See description of register TCCR1A.
  • Bit 2: 0 - CS1 [2: 0]: Clock selection
These bits determine the prescaler source for counter / timer 1, see Figure 16-10 and Figure 16-11.
Table 16-5: Clock selection bit description
CS12CS11CS10description
000Counter / timer 1 is stopped
001clkI / O/ 1 (no prescaler)
010clkI / O/ 8 (with prescaler)
011clkI / O/ 64 (with prescaler)
100clkI / O/ 256 (with prescaler)
101clkI / O/ 1024 (with prescaler)
110External source on T1 pin, falling edge
111External source on T1 pin, rising edge
If an external source is used to clock the counter / timer 1, the clocking also works if the pin is configured as an output. This makes it possible to control the counting function via software.

16.11.3 TCCR1C - control register C

bit76543210
(0x82)FOC1AFOC1B------TCCR1C
accessR / WR / WR.R.R.R.R.R.
Starting value00000000
  • Bit 7 - FOC1A: Force output compare for OC1A
  • Bit 6 - FOC1B: Force output compare for OC1B
The two bits FOC1A and FOC1B are only active if the WGM bits select a non-PWM mode. To ensure compatibility with future modules, these bits must be set to 0 if the counter is operated in a PWM mode. If a logical 1 is written into the FOC1A or FOC1B bits, a compare match is immediately forced. The OC1A or OC1B outputs then change according to the settings of the COM bits. It should be noted that the FOC bits are implemented as enable bits, so that the behavior in the event of a forced compare match is determined by the COM bits.

A forced compare match does not generate any interrupts and does not clear the timer. The FOC bits are always read as 0.

16.11.4 TCNT1 - counting register

bit76543210
(0x85)TCNT1 [15: 8]TCNT1H
(0x84)TCNT1 [7: 0]TCNT1L
accessR / WR / WR / WR / WR / WR / WR / WR / W
Starting value00000000
The two I / O registers TCNT1H and TCNT1L, which together represent the counter / timer 1 TCNT1, give direct access to the 16-bit counter for read and write operations. To ensure that the low and high byte are read and written at the same time when the CPU accesses them, a shadow register (TEMP) is used for the high byte. This shadow register is also used by the other 16-bit registers.

Changing the counter (TCNT1) while the counter is running leads to the risk that a compare match between TCNT1 and the OCR1x registers will be omitted.

When writing to the TCNT1 register, the compare matches are blocked for all comparison units in the next cycle.

16.11.5 OCR1A - comparison register A

bit76543210
(0x89)OCR1A [15: 8]OCR1AH
(0x88)OCR1A [7: 0]OCR1AL
accessR / WR / WR / WR / WR / WR / WR / WR / W
Starting value00000000
The value in OCR1A is constantly compared with the counting register TCNT1. If they are the same, a compare-match interrupt can be triggered and / or a signal curve can be generated on the OC1A pin.

16.11.6 OCR1B - comparison register B

bit76543210
(0x8B)OCR1B [15: 8]OCR1BH
(0x8A)OCR1B [7: 0]OCR1BL
accessR / WR / WR / WR / WR / WR / WR / WR / W
Starting value00000000
The Output Compare Registers contain a 16-bit value that is permanently compared with the value of the counter (TCNT1). A match can be used to trigger an interrupt or to generate an output wave at the OC1x pin.

The Output Compare Registers are 16-bit wide. To ensure that the low and high byte are read and written at the same time when the CPU accesses them, a shadow register (TEMP) is used for the high byte. This shadow register is also used by the other 16-bit registers.

16.11.7 ICR1 - Input Capture Register

bit76543210
(0x87)ICR1 [15: 8]ICR1H
(0x86)ICR1 [7: 0]ICR1L
accessR / WR / WR / WR / WR / WR / WR / WR / W
Starting value00000000
The input capture register is updated with the value of the counter whenever an event occurs on the ICP1 pin or on the output of the analog comparator. The Input Capture Register can also be used to set the TOP value for the counter.

The input capture register is 16-bit wide. To ensure that the low and high byte are read and written at the same time when the CPU accesses them, a shadow register (TEMP) is used for the high byte. This shadow register is also used by the other 16-bit registers. See 16-bit register access.

16.11.8 TIMSK1 - interrupt mask

bit76543210
(0x6F)--ICIE1--OCIE1BOCIE1ATOIE1TIMSK1
accessR.R.R / WR.R.R / WR / WR / W
Starting value00000000
These bits are reserved and are always read as 0.
  • Bit 5 - TICIE1: Counter / timer 1 interrupt release for input capture
If the TICIE1 bit is set and the I bit in the status register (SREG) is also set, the counter / timer 1 input capture interrupt is enabled. The associated interrupt routine is executed when the ICF1 bit is set in the TIFR1 register.
  • Bit 2 - OCIE1B: Counter / timer 1 interrupt release for output compare B
If the OCIE1B bit is set and the I bit in the status register (SREG) is also set, the counter / timer 1 Output Compare B Match Interrupt is enabled. The associated interrupt routine is executed when the OCF1B bit is set in the TIFR1 register.
  • Bit 1 - OCIE1A: Counter / timer 1 interrupt release for output compare A
If the OCIE1A bit is set and the I bit in the status register (SREG) is also set, the counter / timer 1 Output Compare A Match Interrupt is enabled. The associated interrupt routine is executed when the OCF1A bit is set in the TIFR1 register.
  • Bit 0 - TOIE1: Counter / timer 1 interrupt release for counter overflow
If the TOIE1 bit is set and the I bit in the status register (SREG) is also set, the counter / timer 1 overflow interrupt is enabled. The associated interrupt routine is executed if an overflow has occurred in counter / timer 1 and the TOV1 bit is set in the TIFR1 register.

16.11.9 TIFR1 - interrupt flags

bit76543210
(0x36)--ICF1--OCF1BOCF1ATOV1TIFR1
accessR.R.R / WR.R.R / WR / WR / W
Starting value00000000
These bits are reserved and are always read as 0.
  • Bit 5 - ICF1: Counter / timer 1 flag for input capture
The ICF1 bit is set when a capture event occurs on the ICP1 pin. If the ICR1 register is used for the TOP value of the counter, the ICF1 flag is set whenever the counter reaches the TOP value.

The bit is automatically cleared when the associated interrupt routine is executed. Alternatively, the flag can be deleted by writing a logical "1" in the flag.

  • Bit 2 - OCF1B: Counter / timer 1 flag for output compare B
The OCF1B bit is set in the clock cycle after the counter TCNT1 has reached the value of the output compare register B (OCR1B). However, a forced output compare (FOC1B) does not set the OCF1B flag.

The bit is automatically cleared when the associated interrupt routine is executed. Alternatively, the flag can be deleted by writing a logical "1" in the flag.

  • Bit 1 - OCF1A: Counter / timer 1 flag for output compare A
The OCF1A bit is set in the clock cycle after the counter TCNT1 has reached the value of the output compare register A (OCR1A). However, a forced output compare (FOC1A) does not set the OCF1A flag.

The bit is automatically cleared when the associated interrupt routine is executed. Alternatively, the flag can be deleted by writing a logical "1" in the flag.

  • Bit 0 - TOV1: Counter / timer 1 flag for overflow
The setting of this flag depends on the settings of the WGM bits. The TOV1 bit is set in the normal and shortened counting range when an overflow occurs in counter / timer 1; in the case of the shortened counting range in the event of overflow beyond of the comparison value. See the tables on the previous pages for the behavior of the flag in the other cases.

The bit is automatically cleared when the associated interrupt routine is executed. Alternatively, the flag can be deleted by writing a logical "1" in the flag.