What is a computer bus network

System bus

The system bus is used to control, address and transfer data. The system bus has its own signal lines for each task. The system bus is divided into a data bus, address bus and control bus.

Note: What was originally the system bus is now only the connection between processor and chipset. For a long time, this connection was also known as the front-side bus (FSB). Today this connection has a different name depending on the system or system manufacturer.
Because many formerly outsourced functions are integrated into the main processor (CPU) for reasons of speed, the concept of the system-wide system bus is no longer valid. The classic "system bus" no longer exists in today's computer architecture. The architecture usually consists of various serial and parallel bus systems that have been specially designed and developed for the respective requirements. Point-to-point connections are being used more and more frequently. This is due to the fact that more and more functions can be accommodated in a highly integrated manner in just a few modules, thereby increasing the transmission rate between the individual functional units.

Representation of the system bus


The system bus connects the individual components of a computer system. In addition to the processor (CPU), there is a read-only memory (ROM), a working memory (RAM) and input and output units (input and output). The address bus, data bus and control bus run from unit to unit. All units are connected to one another via this bus.
Although there is no longer a system-wide system bus in today's computer systems, the way in which the memory and peripherals are controlled, as described below, has remained the same.

Address bus

The address bus is responsible for the transfer of memory and peripheral addresses. The address from which the data is to be read or where it is to be written is created on the address bus.
The address space designates the addressable memory area. This information shows how many elements can actually be addressed. The number of address lines is a decisive factor for the maximum number of memory locations to be addressed. An address with a length of n bits corresponds to an address space of 2n Elements.

This formula is used to determine the maximum usable memory size that a processor can address (in bytes).

Data bus

The data bus is available for transferring data between the processor, main memory and peripherals. The number of data bus lines determines the number of bits that can be transmitted per cycle.
All modules that can transfer or receive data to the data bus (processor, memory, I / O) are connected to the data bus. The data is released by the processor via a control line for only one module at a time. This means that there can only ever be one data transfer between two modules.

Control bus

The control bus is used to transmit certain signals to the individual components. This tells the assemblies what to do. E.g. take the data from the data bus or place data on the data bus.
The control bus also contains the interrupt lines via which the peripheral devices can signal an interrupt request to the processor. Typically, interrupt requests are generated upon data entry.

The following signals are processed by the control bus:
  • Reading from the RAM
  • Write to the RAM
  • Input from peripheral devices
  • Output to peripheral devices
  • Interrupt signals

Processes on the system bus

Example: ROM reading process

The CPU is to read data from the function module ROM: The CPU ...

  1. ... puts the address of the function module ROM and the memory cell on the address bus.
  2. ... activates the control line READ, whereby the addressed memory cell transfers its content to the data bus.
  3. ... takes over the data from the data bus and deactivates the READ control line. The reading process is now complete.
Example: Write process OUT

The CPU is to write data to the function module OUT: The CPU ...

  1. ... puts the address of the function module OUT on the address bus.
  2. ... puts the data on the data bus.
  3. ... activates the control line WRITE, whereby the function module OUT receives the data from the data bus.
  4. ... deactivates the control line WRITE. The writing process is now complete.

Bus termination


Each address line, each data line and each control line is routed via a bus termination. The pull-up resistor RUP ensures that the bus line is not open and can pick up interfering signals. The terminating resistor RW. is the alternating current resistance / characteristic impedance.
The capacitor ensures that the DC circuit is separated from ground.

Comparison of the address and data bus width of some processors

processorAddress busData bus
808820 bits8 bit
8086 (XT)20 bits16 bit
80286 (AT)24 bit16 bit
80386-SX32 bit16 bit
80368-DX32 bit32 bit
8046832 bit32 bit
Pentium32 bit64 bit
Pentium Pro36 bits64 bit
Pentium MMX32 bit64 bit
Pentium II36 bits64 bit

While the address bus width influences the maximum memory size that a processor can address, the data bus width influences the transmission speed. The clock speed of the data bus also plays a role here.

System bus expansions

Other related topics:

Everything you need to know about computer technology.

Computer technology primer

The computer technology primer is a book about the basics of computer technology, processor technology, semiconductor memory, interfaces, data storage devices, drives and important hardware components.

I want that!

Everything you need to know about computer technology.

Computer technology primer

The computer technology primer is a book about the basics of computer technology, processor technology, semiconductor memory, interfaces, data storage devices, drives and important hardware components.

I want that!