Scientists from Canada and the United States found two ways to expedite the synthesis of transistors based on carbon nanotubes. In the first method the substrate is dipped in the solution for 10 seconds, dried and repeated the procedure. In the second method, the substrate was dripping a solution of nanotubes and allowed to dry. The researchers were able to reduce the time of synthesis of the substrates with two days before to 150 seconds, while maintaining compatibility with modern processes. The chip, with these transistors will consume three times less energy, than conventional silicon devices. Article published in the journal Nature Electronics.
According to the law of scaling of Dennard, reducing the size of transistors and increasing clock frequency of processors to improve its performance. However, reducing the size of transistors increases the cost of the processors and their power consumption. Reducing the size of silicon FETs at the moment does not give significant reduction of energy consumption. To make computing cheaper and more energy efficient, scientists are looking for new materials that can replace silicon and be compatible with the existing silicon electronics.
One of the promising materials for the creation of a new generation of transistors — carbon nanotubes. Their small size — about 1.2 nm in diameter and high speed of the charge carriers allows you to create them on the basis of very large-scale integration, the processing speed which is three times higher and the energy consumption is three times lower than traditional silicon. However, until now, to establish industrial production of transistors based on nanotubes failed.
One of the problems is that such transistors are incompatible with CMOS — technology, which today create most of the integrated circuits. According to CMOS, the chip should be placed transistors with insulated gate and channels of different conduction — electron or hole. Another problem is a large amount of time required for manufacturing such transistors.
In previous papers physics already reported on the establishment of CMOS-compatible transistors with electron conductivity. However, they use the synthesis method did not allow evenly nanotubes on the surface of a large area. Because of this, there were some differences in conductivity and concentration of charge carriers transistors, which are not allowed to use them in the same chip.
A team of researchers from Canada and the United States under the leadership of mindy D. Bishop (Mindy D. Bishop) has developed a new method of applying carbon nanotubes on the surface. With it you can evenly apply the nanotube on the substrate with a diameter of 200 millimeters are now being used in the industrial production of transistors.
The authors took as a basis a method for the deposition of nanotubes from solution, in which the substrate is placed in toluene with dispersed nanotubes in it and kept there for two days. Instead of such prolonged immersion the researchers placed the substrate into the solution for about 10 seconds, and then took it out and dried. Then the process was repeated until the concentration of nanotubes on the substrate has not reached the limit. Deposition of nanotubes by this method took a total of 150 seconds is 1100 times less than required so far.